A data processing system operating asynchronously with one or more memory units has been described in the previously filed U.S. Pat. application Ser. No. 387,523, filed Aug. 10, 1973, now abandoned, refiled as continuation application Ser. No. 646,351 on Jan. 2, 1976 by Sorensen et al. and assigned to the same assignee as this application now issued as U.S. Pat. No. 4,014,006 on Mar. 22, 1977, such previously filed applications being hereby incorporated by reference in this application. In the previously described system, a single common bidirectional data and memory bus was used for data transfers among the memory units, the central processor unit (CPU) and the inut/output (I/O) units. Moreover, the unique data path configuration described therein was devised to interconnect a CPU register file, which register file included a memory address register (MA), with an arithmetic logic unit (ALU), a shifter unit, a separately connected instruction register (IR) and the common bus to provide an optimization of the data transfers among such units and the memory units, thereby improving the overall processing time during many operations. In accordance therewith the system took advantage of the use of an available skew-protected, tri-state, quadriport register file, having its read and write ports uniquely connected to the associated units and to the single data/memory bus and the memory address bus (MADR) so as to provide the desired optimum operation within the operating constraints of the register file.
While the structure and operation of such previously described system has found widespread and effective use in many applications, in many cases it is desirable to improve such operation even further by providing quicker access to addresses in the memory units than is provided in such previous system and to avoid the data transfer constraints imposed by the use of a single common data/memory bus.